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ISL97671A
TABLE 4. OPERATING MODES SELECTED BY DEVICE CONTROL
REGISTER BITS 1 AND 2
For example, the Cbt = 50% duty cycle programmed in the
SMBus/I 2 C Register 0x00 and the PWM frequency is tuned to be
PWM_MD
0
1
X
PWM_SEL
0
0
1
MODE
SMBus/I 2 C and PWM input controlled
(DPST) dimming (Method 3)
SMBus/I 2 C controlled PWM dimming
(Method 1)
PWM input controlled PWM dimming
(Method 2)
200Hz with an appropriate capacitor at the FPWM pin. On the other
hand, PWM is fed with a 1kHz 30% high PWM signal. When
PWM_SEL = 0 and PWM_MD = 0, the device is in DPST operation
where DPST brightness = 15% PWM dimming at 200Hz.
Fault/Status Register (0x02)
This register has 6 status bits that allow monitoring of the backlight
controller’s operating state. Not all of the bits in this register are
The PWM_SEL bit determines whether the SMBus/I 2 C or PWM
input should drive the output brightness in terms of PWM
dimming. When PWM_SEL bit is 1, the PWM input only drives the
output brightness regardless of what the PWM_MD is.
When the PWM_SEL bit is 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted; when
this bit is 1, the PWM dimming is based on the SMBus/I 2 C
brightness setting only. When this bit is 0, the PWM dimming
reflects a percentage change in the current brightness
programmed in the SMBus/I 2 C Register 0x00, i.e., DPST (Display
Power Saving Technology) mode as:
fault related (Bit 3 is a simple BL status indicator). The remaining
bits are reserved and return a “0” when read and ignore the bit value
when written. All of the bits in this register are read-only, with the
exception of bit 0, which can be cleared by writing to it.
? BL_STAT indicates the current backlight on/off status in
BL_STAT (1 if the BL is on, 0 if the BL is off).
? FAULT is the logical OR of THRM_SHDN, OV_CURR, 2_CH_SD,
and 1_CH_SD should these events occur.
? 1_CH_SD returns a 1 if one or more channels have faulted out.
? 2_CH_SD returns a 1 if two or more channels have faulted out.
? When FAULT is set to 1, it will remain at 1 even if the signal
DSPT Brightness = Cbt × PWM
(EQ. 15)
which sets it goes away. FAULT will be cleared when the
Where:
Cbt = Current brightness setting from SMBus/I 2 C Register 0x00
without influence from the PWM
PWM = is the percent duty cycle of the PWM
BL_CTL bit of the Device Control Register is toggled or when a
0 is written into the FAULT bit. At that time, if the fault
condition is still present or reoccurs, FAULT will be set to 1
again. BL_STAT will not cause FAULT to be set .
? The default value for Register 0x02 is 0x00.
REGISTER 0x02
FAULT/STATUS REGISTER
RESERVED
Bit 7 (R)
RESERVED
Bit 6 (R)
2_CH_SD
Bit 5 (R)
1_CH_SD
Bit 4 (R)
BL_STAT
Bit 3 (R)
OV_CURR
Bit 2 (R)
THRM_SHDN
Bit 1 (R)
FAULT
Bit 0 (R)
BIT
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BIT ASSIGNMENT
2_CH_SD
1_CH_SD
BL_STAT
OV_CURR
THRM_SHDN
FAULT
BIT FIELD DEFINITIONS
= Two LED output channels are shutdown (1 = shutdown, 0 = OK)
= One LED output channel is shutdown (1 = shutdown, 0 = OK)
= BL Status (1 = BL On, 0 = BL Off)
= Input Overcurrent (1 = Overcurrent condition, 0 = Current OK)
= Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)
= Fault occurred (Logic “OR” of all of the fault conditions)
FIGURE 31. DESCRIPTIONS OF FAULT/STATUS REGISTER
21
FN7709.3
November 30, 2012
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